1. Field of the Invention
The present invention relates to computers such as personal computers. More specifically, the present invention relates to interfaces and associated operating methods for system management of computer systems.
2. Description of the Related Art
Several software and hardware manufacturing companies in the computer industry, including Intel.TM., Microsoft.TM., and Toshibas.TM., have been leaders in the standardization of system management of personal computers (PCs). These standards are set forth to allow a next generation of Operating Systems to perform a more active role in the management of computer system functions including battery charge control, fan control, and the like. The standard is described in an Advanced Configuration and Power Interface (ACPI) specification, a key element in Operating System Directed Power Management (OSPM). The OSPM and the ACPI apply to all classes of computers, explicitly including desktop, mobile, home, and server computer systems.
The ACPI adapts existing power management software tools including BIOS code, APM APIs, PNPBIOS APIs, and the like into a well-defined power management and configuration system. The ACPI supports an orderly transition from existing (legacy) hardware to ACPI hardware, and allows legacy and ACPI hardware to coexist in a single computer and to become active when appropriate.
New system architectures are designed that stretch the limits of current Plug and Play interfaces. The ACPI adapts existing motherboard configuration interfaces to support these advanced architectures in a more robust, and potentially more efficient manner.
The ACPI-compatible hardware and software implementing operating system (OS) directed power management (OSPM) support include interfaces within a PC to manage the controls defined by the Advanced Power and Configuration Interface Specification (ACPI).
The ACPI specification outlines an interface to an embedded controller. The embedded controller described in the ACPI specification is programmed in a manner similar to the programming of a keyboard interface. A problem with the ACPI-specified embedded controller is that for advanced monitoring capabilities, which are typically utilized in servers, the interface is very slow and interrupt-intensive. The ACPI-compliant embedded controller utilizes approximately one interrupt for the transfer of a single byte.
The ACPI is a relatively new specification so that only fundamental constructs of the embedded controller have been developed. For example, battery management in an ACPI-compliant embedded controller has been implemented with an I.sup.2 C bus controller to communicate with the battery. The I.sup.2 C bus controller is available in an ISA bridge chip from Intel. Currently, the ACPI specification is primarily implemented in portable PC's.
Referring to FIG. 1, which is labeled PRIOR ART, a "standard" host interface 100 to an embedded controller 102, as outlined by the ACPI standard, is shown. The interface is modeled after a standard keyboard controller-style interface and includes a COMMAND/STATUS register and a DATA IN/DATA OUT register. The interface uses an interrupt to signal the HOST processor. Separate simultaneous processes are accommodated on the HOST through the usage of two separate copies of the registers and two separate interrupts. A first interrupt, a System Control Interrupt (SCI) 104, is used by the operating system. A second interrupt, a System Management Interrupt (SMI) 106, is used in System Management Mode (SMM).
The embedded controller and the HOST processor communicate data using control bits in the COMMAND/STATUS register including an input buffer full (IBF) bit and an output buffer full (OBF) bit. The Input Buffer Full (IBF) flag is asserted when the HOST processor has written a byte of data to the command port or data port, but the embedded controller has not yet read byte so that the input buffer is full and data is ready for the embedded controller. The embedded controller reads the status byte, detects the set IBF flag, and reads the data port to get the byte of data written by the HOST processor. After the embedded controller reads the data byte, hardware automatically clears the IBF flag, signaling to the HOST processor that the data was read by the embedded controller and the input buffer of the embedded controller is empty, so that the HOST processor is free to write more data to the embedded controller.
The Output Buffer Full (OBF) flag is asserted when the embedded controller writes a byte of data into the command or data port of the embedded controller so that the output buffer is full and data is ready for the HOST processor. The HOST processor reads the status byte, detects that the OBF flag is set, and reads the data port to get the byte of data that is written by the embedded controller. After the HOST processor reads the data byte, embedded controller hardware automatically clears the OBF flag, signaling the embedded controller that the data has been read by the host computer, the output buffer is empty, and the embedded controller is free to write more data to the host computer.
Thus for each data byte transferred, either from the HOST processor to the embedded controller or from the embedded controller to the HOST processor, the COMMAND/STATUS register is read and a either the IBF or the OBF bit is checked to determine whether bit has gone to zero. The status of the transfer buffer must be checked before the next byte can be written.
The ACPI standard interface supports a burst data transfer mode that allows the operating system or system management interrupt handler to quickly read and write several bytes of data at a time without the overhead of handling system command interrupts between the commands. Assertion of the burst enable mode bit sets up the controller to guarantee a response time within a defined range, such as up to 5 microseconds.
The burst mode is useful when the controller simultaneously executes multiple tasks including a task performing communication between the controller and a separate processor. However, in the burst mode, the IBF bit or the OBF bit, depending on the direction of the transfer, must still be checked for the transfer of each byte. In the burst enable mode, the microcontroller temporarily discontinues all other processing to handle transmitted data, transfers the data, typically performs an action on the data, then returns to the discontinued processing. Each byte must be read from a transmission buffer and the data transmission flag, either the IBF or the OBF, must be monitored for the handling of each byte. Data bytes are transferred at regular intervals of approximately 1 millisecond.
Other custom interfaces to embedded controllers exist that do not conform to the ACPI standard.
What is needed is an ACPI-compliant interface that reduces data transfer overhead and increases data transfer rate. What is further needed is a faster interface between a host processor and an embedded processor.